package bottlerocket
import chisel3._
import chisel3.util._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.util._
import freechips.rocketchip.config._


class DMIReqAsyncQueue(implicit p: Parameters) extends Module
{
  val io = IO(new CrossingIO(new DMIReq(p(DebugModuleParams).nDMIAddrSize)))

  val queue = Module(new AsyncQueue(new DMIReq(p(DebugModuleParams).nDMIAddrSize), 1))
  io <> queue.io
}

class DMIRespAsyncQueue(implicit p: Parameters) extends Module {
  val io = IO(new CrossingIO(new DMIResp))
  val queue = Module(new AsyncQueue(new DMIResp, 1))
  io <> queue.io
}
